The present invention is directed to an electrically programmable and erasable device and a method for making the same. The electrically programmable memory device can be of the type that is commonly called Electrically Erasable Programmable Read Only Memory (EEPROM). More particularly, the present invention relates to the structure and manufacture of a single transistor EEPROM cell suitable for use in high density memory devices.
EEPROM devices and methods for making such devices are well known in the art. In general, an EPROM or an EEPROM is characterized by a "floating gate" and an electrical connection termed a "control gate", both of which are fabricated out of polycrystalline silicon doped with an appropriate doping material to render the polycrystalline conductive. A typical doping material is phosphorus.
The floating gate is separated from a substrate region by a gate oxide layer of insulating material. The substrate region includes symmetrical source and drain regions which define a channel.
The floating gate and the control gate are separated by a layer of insulating material, typically silicon dioxide (SiO.sub.2). The principle upon which the EPROM or EEPROM device operates is that electrons, or charge, are stored on the "floating gate" in a capacitive manner. Thus, the dielectric layer between the floating gate and the control gate is important.
In the prior art (see for example, U.S. Pat. No. 4,203,158 and W. S. Johnson et al. ISCCC Digest of Technical Papers, pp. 152-153 (Feb., 1980)), the floating gate is formed by reacting SiH.sub.4 in a low pressure chemical vapor deposition chamber and then doped with POCl.sub.3 in a separate doping cycle.
A layer of silicon dioxide is then deposited or thermally grown on the doped polycrystalline layer of silicon. The layer of silicon dioxide is typically approximately 750 angstroms. Generally, a high oxidation temperature (greater than 1050 degrees C.) and heavier phosphorus doping are required to achieve better interpoly quality and breakdown capability. However, oxidation at high temperature on heavily-doped polysilicon involves several drawbacks, such as: (1) outgassing during interpoly oxidation which causes autodoping on the wafer; and (2) oxidation enhanced diffusion of phosphorus from the floating gate to the tunnel oxide, which forms trapping centers in the oxide. The electron trapping collapses the threshold window EEPROM cell at 10 cycles. (See: R. B. Marcus et al., J. Electrochem. Soc., p. 1282, June, 1982; K. Saraswat et al., Computer-Aided Design of Integrated Circuit Fabrication Process for VLSI Device, p. 244290, July, 1981.) Thus, current devices exhibit low cyclability for program and erase operations.
Finally, the second layer of doped polycrystalline silicon is formed on top of the insulating layer of SiO.sub.2.
Because the insulating layer of silicon dioxide is on the order of 750 angstroms, the typical write or erase voltage, i.e., the voltage which is needed to place charge on or to remove charge from the floating gate, has been high, i.e., in excess of 20 volts. In turn, this places shrinkage limits on gate oxide thickness, junction depth and die size.
Silicon nitride (Si.sub.3 N.sub.4) has also been used as an insulating layer of dual dielectric (thermal oxide with silicon nitride on it) between the floating gate and the control gate connection. Silicon nitride has the property that it is more dense than silicon dioxide and, therefore, affords higher capacitive coupling between the floating-gate and the control gate. A typical dual dielectric between the floating gate and the control gate is composed of 500 angstroms oxide and 400 angstroms nitride. However, even with the use of silicon nitride as the insulting layer, the write and erase voltage is still relatively high, in excess of 18 volts. High erase and program voltages for conventional EEPROM devices are of major concern Such a requirement has led to the need for a separate high voltage supply when operating the devices, or for the use of special voltage multiplying circuitry within the device for boosting the supply voltage to the requisite program and erase levels.
An additional drawback is that current EEPROM structures, when used in a memory array, require additional control circuitry to isolate individual storage cells from one another. This increases the device geometry. For example, given the requirement of a control transistor for each EEPROM cell, the equivalent space requirement for a conventional EEPROM cell is 165 square microns